ラベル: arch-riscv の Pull Request の一覧を表示します。上から新しい順に表示されています。
- #136297 [RISC-V] Fix 64-bit constant truncation on LLP64 hosts
- #134057 [NativeAOT] Fast interface dispatch helper for riscv64
- #134051 [NativeAOT] Read the byte-packed LSDA offsets without a misaligned load
- #133380 Probe {riscv,loongarch,arm}64 virtual memory address
- #132741 Fix RISC-V JIT opcode format mismatch
- #132134 DispatchResolve: Avoid clobbering t1 in RhpInterfaceDispatch
- #128799 Detect and use zicond in ifconversion on riscv64
- #129887 [LoongArch64] Apply fixes for coreclr-interp on linux-loongarch64.
- #130186 JIT: initialize emitCurIG at declaration
- #129854 Align RV64's cordbregisterset with LA64 and arm64
- #130015 Preserve throw kind across GetThread
- #128374 Fix clobbering of RhpInterfaceDispatchSlow arguments on riscv64
- #128066 Fix runtime-async on riscv64 with R2R
- #127919 Apply fixes for coreclr-interp on linux-riscv64
- #126566 [RISC-V] Use fine-grained fence variants for memory barriers
- #125446 Improve runtime-async support on linux-riscv64
- #125653 Fix inner build of community archs
- #125353 Sync cDAC's RV64/LA64 implementations with ARM64
- #122485 [RISC-V] Enable instruction printing for the Generate code phase in JIT dumps
- #122501 [RISC-V] Fix 64-bit offset handling in emitLoadImmediate
- #122088 [RISC-V] Enhance the utilization of sh1/2/3add(.uw) instructions
- #122382 [RISC-V] correct comments in emitLoadImmediate
- #121739 [RISC-V] Enable constant CSE in RISCV64
- #122727 Handle more async nodes on community platforms
- #122589 [RISC-V] Comment and formatting cleanup in codegenriscv64